Method and apparatus for partial refreshing of DRAMS

ABSTRACT

Memory devices, refresh logic and approaches to selectively refresh each row of memory cells within a memory device depending on whether or not each is marked as having data to be preserved.

BACKGROUND

Computer systems continue to be designed to meet the two often opposinggoals of increased speed and decreased power consumption. The struggleto meet both goals becomes quite evident in the case of electronicdevices such as portable computer systems, including notebook andhandheld computers. As ever more uses for such electronic devices arefound, there is a need for ever more processing capability, includingfaster processors, more memory, etc. However, at the same time, as evermore uses for such devices are found, there is an increasing desire tomake them ever more portable so that such devices become easier totransport to places where they can be used in such new found ways.

This struggle has resulted in efforts to find ways to decrease theamount of power required by each of the components of such electronicdevices, including memory devices. Known approaches include creatingreduced power modes (commonly referred to as “sleep modes” or“hibernation modes”) for such electronic devices to enter into when notactively being used. DRAM (dynamic random access memory) devices havebeen created with lower power modes, including what is commonly referredto in the DRAM device industry as “self refresh” mode. In self refreshmode, interactions between DRAM devices and other components areminimized, including interactions where commands are regularlytransmitted to DRAM devices to perform the function of refreshing memorycells within a DRAM device to prevent loss of data stored within thosememory cells. Self refresh modes entail using a minimal amount of logicbuilt into a DRAM device to allow the DRAM device to autonomously carryout the function of refreshing the DRAM device's memory cells.

However, such approaches to reducing DRAM device power consumption havenot addressed the problem of the unnecessary wasting of power to refreshlarge quantities of memory cells not containing data to be preserved,even in reduced power modes such as self refresh mode.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features, and advantages of the present invention will beapparent to one skilled in the art in view of the following detaileddescription in which:

FIG. 1 is a block diagram of an embodiment employing a memory device.

FIG. 2 is a block diagram of an embodiment employing a computer system.

FIG. 3 is a flow chart of a method of an embodiment.

FIG. 4 is a flow chart of a method of another embodiment.

FIG. 5 is a flow chart of a method of still another embodiment.

FIGS. 6 a and 6 b are timing diagrams of embodiments employing a memorybus.

FIG. 7 is a block diagram of another embodiment employing a computersystem.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, numerousdetails are set forth in order to provide a thorough understanding ofembodiments of the present invention. However, it will be apparent toone skilled in the art that these specific details are not required inorder to practice the present invention as hereinafter claimed.

Embodiments of the present invention concern incorporating support forlimiting the refreshing of memory cells of a DRAM device to onlyportions of a DRAM device having memory cells containing data to bepreserved, and thereby reduce the amount of power used to refresh memorycells not containing such data. Although the following discussioncenters on DRAM devices, it will be understood by those skilled in theart that the present invention as hereinafter claimed may be practicedin support of any type of memory device having cells in need of beingrefreshed or otherwise maintained at regular intervals in order topreserve their contents. It will also be understood by those skilled inthe art that although the following discussion centers on memory devicesin which memory cells are organized in two dimensional arrays of rowsand columns, the memory cells may be organized in any of a number ofways, including into banks and with or without interleaving, arrays ofmore than two dimensions, content-addressable, etc. Also, although atleast part of the following discussion centers on memory within computersystems, it will be understood by those skilled in the art that thepresent invention as hereinafter claimed may be practiced in connectionwith other electronic devices or systems having memory devices.

FIG. 1 is a simplified block diagram of one embodiment employing amemory device. Memory device 100 is, at least in part, made up of memoryarray 110, control logic 130, row address decoder 134, column addressdecoder 136, data column multiplexer 138, external control interface154, external address interface 156, and external data interface 158.Those skilled in the art of the design of memory devices, including DRAMdevices, will readily recognize that FIG. 1 provides a relatively simpledepiction of components making up a DRAM device, and that the exactarrangement and configuration of components within a DRAM device may bereduced, augmented or otherwise altered without departing from thespirit and scope of the present invention as hereinafter claimed.Specifically, although memory device 100 is depicted as having only onememory array 110, suggesting that memory device 100 has only one “bank”of memory cells organized in a single two dimensional array for the sakeof simplicity of discussion, it will be understood by those skilled inthe art that the memory cells of memory device 100 may be organized inany of a number of ways, including having more than one memory array toprovide more than one bank, or having a single memory array configuredto provide the functional equivalent of multiple banks.

External control interface 154, external address interface 156 andexternal data interface 158, together, provide an interface betweenmemory device 100 and external devices (not shown) that are attached tomemory device 100. Through external control interface 154, which iscoupled to control logic 130, memory device 100 receives commands tocarry out read, write and other operations. Through external addressinterface 156, which is coupled to control logic 130, memory device 100receives addresses specifying which memory cell(s) within memory array110 are involved in read, write and other operations. Through externaldata interface 158, which is coupled to at least data column multiplexer138, memory device 100 both transmits data retrieved from memory array10 to external devices and receives data sent by external devices to bestored in memory array 110.

Control logic 130 coordinates the carrying out of commands received viaexternal control interface 154, either with or without addresses and/orother information received via external address interface 156. Thememory cells of memory array 110 are organized into a two dimensionalarray of rows and columns, such that control logic 130 selects portionsof memory array 10 to be accessed to carry out a read, write or otheroperation by sending row addresses to row address decoder 134 and columnaddresses to column address decoder 136, both of which are coupled tocontrol logic 130. Row address decoder 134 decodes the row addressreceived from control logic 130 and uses the decoded row address toselect a row of memory cells within memory array 110 for access.Similarly, column address decoder 136 decodes the column addressreceived from control logic 130 and uses the decoded column address tocontrol data column multiplexer 138 (to which column address decoder 136is coupled) to select memory cell(s) from the row of memory cellsselected by row address decoder 134 for access.

Making up part of control logic 130 is refresh control logic 140 whichselectively carries out refresh operations to refresh rows of memorycells within memory array 110 that are marked as having data to bepreserved in response to requests to carry out refresh operations.Whether a refresh operation is requested as a result of receiving acommand from an external device or in response to the passage of apredetermined interval of time triggering an internal request, refreshcontrol logic 140 first determines if a row requested to be refreshed ismarked as having data to be preserved. If a row requested to berefreshed is not marked as having data to be preserved, refresh logic140 does not carry out the refresh operation on that row (in essence,refresh logic 140 “ignores” the request), thereby avoiding unnecessarilyusing power to refresh a row that does not have data that is to bepreserved. Otherwise, if a row requested to be refreshed is marked ashaving data to be preserved, then refresh control logic 140 uses rowaddress decoder 134 to select the row of memory cells, requested to berefreshed in a manner not unlike how a row of memory cells is selectedto be accessed as part of a read or write operation. The selection andmarking of rows as either having data to be preserved, or not, iscarried out by an external device (not shown) to which memory device 100is coupled, and from which memory device 100 receives commands causingone or more rows to be marked as either having data to be preserved ornot.

When memory device 100 operates in a non-reduced power mode, refreshcontrol logic 140 selectively carries out commands received via externalcontrol interface 154 from an external device to refresh one or morerows of memory cells within memory array 110. In an embodiment where acommand received via external control interface 154 to carry out arefresh operation is accompanied by an indication through externalcontrol interface 154 and/or external address interface 156 of aspecific row to be refreshed within memory array 110, the row address ofthe specified row is provided to row address decoder 134 to select thespecified row for refreshing if the row is marked as having data to bepreserved. In another embodiment where a command received via externalcontrol interface 154 to carry out a refresh is not accompanied by anindication of a particular row to be refreshed, counter 142 withinrefresh control logic 140 provides a row address for a row to berefreshed, and this row address from counter 142 is provided to rowaddress decoder 134 to select a row for refreshing if that row is markedas having data to be preserved. Regardless of whether or not that rowwas marked as having data to be preserved, counter 142 is thenincremented so as to provide another row address for use in response toa subsequent occurrence of such a refresh command in which no row isspecified.

While memory device 100 operates in a reduced power mode, such as“self-refresh” mode, refresh control logic 140 selectively carries outthe refreshing of rows of memory cells, autonomously, without promptingvia commands received from an external device. In such a reduced powermode, counter 142 within refresh control logic 140 provides a rowaddress for a row to be refreshed, and this row address is provided torow address decoder 134 to select a row for refreshing if that row ismarked as having data to be preserved. Regardless of whether a row ismarked as having data to be preserved, or not, counter 142 isincremented to provide another row address for use in a subsequentrefresh operation.

In some embodiments, marking buffer 144 makes up part of refresh controllogic 140 and maintains marking data concerning which rows of memorycells within memory array 110 are marked as having data to be preservedand which rows are not, and refresh control logic 140 accesses markingbuffer 144 to determine if a refresh operation should be performed on agiven row, or not. In some variations of such embodiments, an externaldevice coupled to memory device 100 transmits a command to mark one ormore rows of memory device 100, using a combination of control linescoupled to external control interface 154 and address lines coupled toexternal address interface 156 to select marking buffer 144 to bewritten to with marking data that marks one or more of the rows withinmemory array 110 as having data to be preserved, or not. It may be thatmarking data is provided to memory device 100 using available controland/or address lines coupled to external control interface 154 and/orexternal address interface 156, or alternatively, it may be that markingdata is provided to memory device using data lines coupled to externaldata interface 158.

In other embodiments, one or more rows of memory cells within memoryarray 110 are allocated to maintain marking data indicating which rowsare marked as having data to be preserved and which rows are not. Insome variations of such embodiments, an external device coupled tomemory device 100 transmits a write command to write at least a portionof a row in which marking data is kept with marking data indicating thatone or more rows has data to be preserved, or not. Such a write commandmay follow a protocol and have timings similar to those employed inwrite commands for the normal writing of data to other memory cellswithin memory device 100 that are not used to store marking data.Alternatively, in other variations, an external device coupled to memorydevice 100 transmits a command to mark one or more rows of memory device100, using a combination of control lines coupled to external controlinterface 154 and address lines coupled to external address interface156 to select a row and/or column(s) within a row to be written withmarking data that marks one or more rows as having data to be preserved,or not. Such a command may be configured with a protocol and/or timingsdiffering from those of a normal write command in an effort reducecomplexity and/or the amount of time required to transmit the command tomemory device 100, perhaps by avoiding the use of data lines coupled toexternal data interface 158.

In embodiments using one or more rows of memory cells within memoryarray 110 to store marking data, it may be deemed desirable for refreshcontrol logic 140 to at be at least partially made up of marking buffer144 to serve as a type of cache for marking data read from one or moreof the rows used to store marking data. It may be that accessing a rowto obtain marking data as a prelude to every possible refresh operationto determine whether or not a refresh operation should actually becarried is deemed to take too long and/or deemed to use too much power.Therefore, a row storing marking data may be accessed to read at least aportion of the marking data within that row and store a copy in markingbuffer 144. To accommodate such use of marking buffer 144, it may bedesirable for marking buffer 144 to be coupled more directly to memoryarray 110 than external data interface 158 (which is coupled to memoryarray 110 through data column multiplexer 138) so that more of thecolumns of data from a selected row having marking data are madeavailable to marking buffer 144 to store a copy of marking data thanmight be possible were marking buffer 144 coupled to memory array 110through data column multiplexer 138. Alternatively, it may be deemedundesirable to provide marking buffer 144 within refresh control logic140 as a result of concerns over the amount of power required tomaintain a copy of marking data within marking buffer 144. Indeed, itmay actually prove to be more desirable to obtain marking from a rowwithin memory array 110 as a prelude to every possible refreshoperation, and in such cases, marking buffer 144 may, indeed, be coupledto memory array 110 through data column multiplexer 138.

FIG. 2 is a block diagram of one embodiment employing a computer system.Computer system 200 is, at least in part, made up of CPU (centralprocessing unit) 210, system logic 220, and memory devices 250 a-250 c.System logic 220 is coupled to CPU 210 and performs various functions insupport of the execution of instructions by CPU 210 including providingCPU 210 with access to memory devices 250 a-250 c to which system logic220 is also coupled through memory controller 240 within system logic220. CPU 210, system logic 220 and memory devices 250 a-250 c make up aform of core for computer system 200 capable of supporting the executionof machine readable instructions by CPU 210 and the storage of data,including instructions, within memory devices 250 a-250 c.

In various embodiments, CPU 210 could be any of a variety of types ofCPU including a CPU capable of executing at least a portion of thewidely known and used “×86” instruction set, and in other variousembodiments, there could be more than one CPU. In various embodiments,memory devices 250 a-250 c could be any of a variety of types of DRAMincluding fast page mode (FPM), extended data out (EDO), single datarate (SDR) or double data rate (DDR) forms of synchronous dynamic RAM(SDRAM), RAM of various technologies employing a RAMBUS™ interface, etc.Memory controller 240 provides logic 220 with an appropriate interfacefor memory device 250 a-250 c, whatever the DRAM type. Despite the widevariety of possible types of DRAM, at least a portion of the memorycells of memory devices 250 a-250 c are organized in rows and columns intwo dimensional memory arrays, such as memory arrays 251 a-251 c. Toaccess a memory cell in any of memory arrays 251 a-251 c, at least a rowaddress to select a row of memory cells from among multiple rows makingup an array, and a column address to select a subset of the memory cellsof the selected row for access must be specified. As those skilled inthe art will recognize, the depiction of a triplet of memory devices inFIG. 2, namely memory devices 250 a-250 c, is but an example of a memorysystem that could accompany a CPU, and that a larger or smaller numberof memory devices could be used without departing from the spirit andscope of the present invention as hereinafter claimed.

In some embodiments, system logic 220 is coupled to and provides CPU 210with access to storage device 260 by which data and/or instructionscarried by storage media 261 may be accessed. Indeed, in someembodiments, storage media 261 carries machine-accessible instructionsto be executed by CPU 210 to cause CPU 210 to mark one or more rowswithin memory devices 250 a-250 c as either containing data to bepreserved, or not, as will be described. Storage media 261 may of any ofa wide variety of types based on any of a wide variety of technologiesas those skilled in the art will understand, including CD or DVD ROM,magnetic or optical disk, magneto-optical disk, tape, semiconductormemory, characters or perforations on paper or other material, etc.

In some embodiments, nonvolatile memory device 230 is coupled to systemlogic 220 (or other part of computer system 200) and provides storagefor an initial series of instructions executed at a time when computersystem 200 is either “reset” or initialized (for example, when computersystem 200 is “turned on” or “powered up”) to perform tasks needed toprepare computer system 200 for normal use. In some variations of suchembodiments, upon initialization or resetting of computer system 200,CPU 210 accesses nonvolatile memory device 230 to retrieve instructionsto be executed to prepare memory controller 240 for normal use inproviding CPU 210 with access to memory devices 250 a-250 c. It may bethat these same retrieved instructions are executed to prepare systemlogic 220 for normal use in providing access to storage device 260 andwhatever form of storage media 261 may be used by storage device 260.

Regardless of the source of a sequence of instructions to be executed byCPU 210 at the time of initialization or reset of computer system 200,CPU 210 is caused to initialize memory devices 250 a-250 c for use,including configuring refresh logic 254 a-254 c and accompanying storagefor marking data to mark row(s) of memory within at least one of memorydevices 250 a-250 c as either having data to be preserved through thecarrying out of refresh operations, or not. In one embodiment whererefresh logic 254 a of memory device 250 a incorporates marking buffer255 a to store marking data specifying which rows of memory cells withinmemory array 251 a contain data to be preserved, CPU 210 may be causedby the execution of a sequence of instructions to use memory controller240 to transmit commands and/or data to memory device 250 a toinitialize entries within marking buffer 255 a to a state where no rowswithin memory array 251 a are marked as having data to be preserved. Inanother embodiment where refresh logic 254 a incorporates marking buffer255 a as a cache for marking data obtained from one or more rows withinmemory array 251 a, CPU 210 may be caused to cooperate with memorycontroller 240 to choose which row(s) of memory array 251 a will be usedto store marking data and/or may be caused to initialize memory cells ofrow(s) to be used to store marking data to a state where rows withinmemory array 251 a are marked as not having data to be preserved. Instill another embodiment where refresh logic 254 a does not incorporatea marking buffer such as marking buffer 255 a, CPU 210 may also becaused to choose rows for use in storing marking data and/orinitializing memory cells in rows used to store marking data to a statewhere rows within memory array 251 a are marked as not having data to bepreserved.

During normal operation of computer system 200, CPU 210 executesinstructions causing CPU 210 to write data (perhaps includinginstructions) into one or more rows making up a memory array within amemory device, such as memory array 251 a of memory device 250 a. Priorto or coincident with writing such data into a row within memory device250 a, CPU 210 is further caused to transmit a command through memorycontroller 240 to memory device 250 a to mark the row into which suchdata is being written as having data to be preserved. In an embodimentwhere marking data is stored in a buffer separate from memory array 251a, such as marking buffer 255 a, a portion of marking buffer 255 a willbe written to mark that row as having data to be preserved. In anotherembodiment where marking data is stored in row(s) within memory array251 a, a portion of a row in which marking data is stored will bewritten to mark the row into which data is being written as having datato be preserved. As a result, when refresh logic 254 a is eithercommanded by memory controller 240 to refresh that row, specifically, orwhen a counter within refresh logic 254 a provides a row addressspecifying that row at a time when a refresh operation is to be carriedout, refresh logic 254 a will obtain the marking data corresponding tothat row, will determine that a refresh operation should actually becarried out so as to refresh that row, and will carry out a refreshoperation on that row.

During normal operation of computer system 200, CPU 210 executesinstructions causing CPU 210 to transmit a command through memorycontroller 240 to memory device 250 a to mark a row as not having datato be preserved. In an embodiment where marking data is stored in abuffer separate from memory array 251 a, such as marking buffer 255 a, aportion of marking buffer 255 a will be written with a value markingthat row as not having data to be preserved. In another embodiment wheremarking data is stored in one or more rows within memory array 251 a, aportion of a row in which marking data is stored will be written with avalue marking that row as not having data to be preserved. As a result,when refresh logic 254 a is either commanded by memory controller 240 torefresh that row, specifically, or when a counter within refresh logic254 a provides a row address specifying that row at a time when arefresh operation is to be carried out, refresh logic 254 a will obtainthe marking data corresponding to that row, will determine that arefresh operation should not be carried out to refresh that row, andwill refrain from carrying out a refresh operation on that row.

In some embodiments, when computer system 200 is in a reduced powerstate, memory devices making up computer system 200, such as memorydevice 250 a, receive a command from memory controller 240 to enter areduced power state such as a self refresh state in which at least someof the interactions taking place between memory controller 240 andmemory device 250 a during normal operation of computer system 200 in anon-reduced power state cease. During such a self-refresh state, memorydevice 250 a must autonomously carry out refresh operations to refreshrows of memory cells within memory array 251 a, and requests to carryout a refresh operation to refresh a given row may be generated by acounter at a predetermined interval of time within refresh logic 254 a,instead of being received from memory controller 240. In response toeach request to carry out a refresh operation to refresh a row for whichthe counter has generated a row address, refresh logic 254 a accessesmarking data, whether within a specialized buffer such as marking buffer255 a or within rows allocated within memory array 251 a, to determineif the row that has been requested to be refreshed is marked as havingdata to be preserved. If the row for which a request has been made tocarry out a refresh operation is marked as having data to be preserved,then the refresh operation is carried out, thereby helping to ensurethat the contents of that row are not lost. Otherwise, if the row forwhich such a request has been made is not marked as having data to bepreserved, then the refresh operation is not carried out.

FIG. 3 is a flow chart of embodiments. As data that is to be preservedis being written to a row of memory cells in a memory device, or as datathat is to be preserved is about to be written to a row of memory cellsat 310, that row is marked as having data to be preserved at 320 if thatrow is not already so marked. In one embodiment, a CPU executes a seriesinstructions making up a portion of monitoring software that at leastmonitors accesses made to a memory device by the CPU as the CPU executesanother series of instructions, and the monitoring software causes theCPU to mark one or more of those rows of as having data to be preserved.

FIG. 4 is another flow chart of embodiments. During the normal operationof an electronic device, as a row marked as having data to be preservedceases to have data that actually is to be preserved at 410, that row ismarked as not having data to be preserved at 420. In one embodiment, aCPU executes a series instructions making up a portion of monitoringsoftware that at least monitors the deallocation of locations of blocksof memory by another series of instructions being executed by the CPU,and the monitoring software causes the CPU to mark one or more of rowsof as not having data to be preserved as the deallocation of locationsof blocks of memory result in one or more rows no longer actually havingdata to be preserved.

FIG. 5 is still another flow chart of embodiments. At 510, a request torefresh a row of memory cells within memory device is received. In someembodiments, this request is made by a device external to a memorydevice, and in other embodiments, this request is generated by a counterwithin a memory device providing row addresses of rows to refreshed atregular intervals, such as when a memory device is in a reduced powermode (such as a “self refresh” mode) At 520, a check is made as towhether or not that row is marked as having data to be preserved. If therow is marked as having data to be preserved, then the a refreshoperation is carried out on that row at 530.

FIGS. 6 a and 6 b are timing diagrams of embodiments employing thetransmission of signals across a memory bus. Both FIGS. 6 a and 6 bdepict the transmission of a marking command to one or more memorydevices to mark a row of memory cells as either having data to bepreserved, or not. Although these figures and the accompanyingdiscussion center on embodiments of memory buses on which transactionstake place that are synchronized to a clock signal, it will be readilyunderstood by those skilled in the art that other embodiments may employother forms of timing coordination or may be asynchronous.

Referring to FIG. 6 a, in one embodiment configured to have timingscompatible with one or more known SDRAM interfaces, a marking command isembedded within an activate command, creating a combined command to oneor more memory devices to both activate a specific row for access, andmark that row as either having data to be preserved, or not. AlthoughFIG. 6 a and this accompanying discussion focus on embedding a markingcommand within an activate command, other embodiments may entailembedding a marking command within one or more other possible commands.In some variations of such an embodiment, an additional command signalline may be added to a preexisting set of command signal lines normallyused with known SDRAM interfaces. Such an additional signal line maysimply be used to double the number of different commands that can bebinary encoded on the now increased set of command signal lines.Alternatively, such an additional signal line may solely serve thepurpose of adding marking commands as embedded commands to any of anumber of possible preexisting commands.

The actual transmission of the activate command with embedded markingcommand may be preceded by a predetermined number of clock transitionson the CK and −CK signal lines between time points 687 and 688 in whichno transmission of commands, addresses or data takes place, if needed,depending on the timing requirements of a given SDRAM interface and/ormemory device in which the row to be marked is located. The activatecommand and embedded marking command are transmitted at time point 688,and coincident with the transmission of these commands in one variationof such an embodiment, bank address signals BA0 and BA1 transmit thebank address of the bank in which the affected row is located (if thegiven memory device(s) have multiple banks), and address signals A0-A11are used to specify the affected row within that bank. Anotherpredetermined number of clock transitions of the CK and −CK signal linesbetween time points 288 and 289 in which, again, no activity occurs mayfollow the transmission of the precharge command, if needed.

Referring to FIG. 6 b, in another embodiment similar to that depicted inFIG. 6 a, and also configured to have timings compatible with one ormore known synchronous DRAM interfaces, a marking command is embeddedwithin a data access command, such as a read or write command, creatinga combined command to one or more memory devices to both read or writedata, and mark the row involved in the data access as either having datato be preserved, or not. Although FIG. 6 b and this accompanyingdiscussion focus on embedding a marking command within a data accesscommand, other embodiments may entail embedding a marking command withinone or more other possible commands.

The actual transmission of a data access command with embedded markingcommand may again be preceded and/or followed by predetermined numbersof clock transitions on the CK and −CK signal lines between time points687 and 688, and/or time points 688 and 689, respectively, in which notransmission of commands, addresses or data takes place, if needed,depending on the timing requirements of a given SDRAM interface and/ormemory device in which the row to be accessed and marked is located. Thedata access (read or write) command is transmitted at time point 688,and coincident with the transmission of this command in one variation ofsuch an embodiment, bank address signals BA0 and BA1 transmit the bankaddress of the bank in which the affected row is located (if the givenmemory device(s) have multiple banks), and address signals A0 up to A9(depending on the number of available columns) are used to specify thecolumn(s) within the affected row within that bank to be accessed.

Also coincident with the transmission of the data access command is thetransmission of a high state on address signal A11, thereby indicatingthat a marking command to mark the affected row either as having data tobe preserved, or not, is embedded within the data access command. Insome variations of such an embodiment, there may be provided a way ofindicating whether the embedded marking command is meant to mark theaffected row as having data to be preserved, or not. Alternatively, inother variations of such an embodiment, such a use of address signal A11may be made as part of a protocol in which embedding a marking commandwith a write command is to be interpreted as a command to mark theaffected row as having data to be preserved, while embedding a markingcommand with a read command is to be interpreted as a command to markthe affected row as not having data to be preserved. Further coincidentwith the transmission of the data access command may be the transmissionof a high state on address signal A10, thereby indicating that an autoprecharge command to close the row after the data access has beencarried out may have been embedded within the data access command, aswell.

In the embodiments depicted in FIGS. 6 a and 6 b, the choices of whichcommand and/or address signal lines may be used to transmit a markingcommand were made to promote interoperability with known synchronousDRAM interfaces, including, but not limited to, the currently widelyused DDR variants of synchronous DRAM interfaces. Despite references tothe use of a specific signal line, such as address line A11, thoseskilled in the art will readily recognize that any combination ofcommand and/or address signal lines may be employed for the purpose oftransmitting a marking command and/or providing interoperability withexisting DDR variants without departing from the spirit and scope of thepresent invention as hereinafter claimed.

FIG. 7 is a block diagram of another embodiment employing a computersystem. Not unlike computer system 200 of FIG. 2, computer system 700is, at least in part, made up of CPU 710, system logic 720, and memorydevices 750 a-750 c. System logic 720 is coupled to CPU 710 and performsvarious functions in support of the execution of instructions by CPU 710including providing CPU 710 with access to memory devices 750 a-750 c towhich system logic 720 is also coupled through memory controller 740within system logic 720 and memory bus 780. CPU 710, system logic 720and memory devices 750 a-750 c make up a form of core for computersystem 700 capable of supporting the execution of machine readableinstructions by CPU 710 and the storage of data, including instructions,within memory devices 750 a-750 c.

As was the case with computer system 200, in various embodiments ofcomputer system 700, CPU 710 could be any of a variety of types of CPU,memory devices 750 a-750 c could be any of a variety of types of DRAMand memory controller 740 provides logic 720 with an appropriateinterface for memory device 750 a-750 c through memory bus 780, whateverthe DRAM type. As those skilled in the art will recognize, the depictionof a triplet of memory devices in FIG. 7, namely memory devices 750a-750 c, is but an example of a memory system that could accompany aCPU, and that a larger or smaller number of memory devices could be usedwithout departing from the spirit and scope of the present invention ashereinafter claimed.

In some embodiments, system logic 720 is coupled to and provides CPU 710with access to storage device 760 by which data and/or instructionscarried by storage media 761 may be accessed, and when executed by CPU710, may cause CPU 710 to mark one or more rows within memory devices750 a-750 c as either containing data to be preserved, or not, as willbe described. Storage media 261 may of any of a wide variety of typesbased on any of a wide variety of technologies as those skilled in theart will understand. In some embodiments, nonvolatile memory device 730is coupled to system logic 720 (or other part of computer system 700)and provides storage for an initial series of instructions executed at atime when computer system 700 is either reset or initialized to performtasks needed to prepare computer system 700 for normal use, which mayentail preparing memory controller 740 for normal use in providing CPU710 with access to memory devices 750 a-750 c, and/or preparing systemlogic 720 for normal use in providing access to storage device 760 andwhatever form of storage media 761 may be used by storage device 760.

Regardless of the source of a sequence of instructions to be executed byCPU 710 at the time of initialization or reset of computer system 700,CPU 710 is caused to initialize memory devices 750 a-750 c for use,including configuring memory controller 740 and marking buffer 745within memory controller 740 to mark row(s) of memory within at leastone of memory devices 750 a-750 c as either having data to be preservedthrough the carrying out of refresh operations, or not. CPU 710 may becaused by the execution of a sequence of instructions to initializeentries within marking buffer 745 to a state where no rows within one ormore of memory arrays 751 a-751 c are marked as having data to bepreserved.

During normal operation of computer system 700, CPU 710 executesinstructions causing CPU 710 to write data (perhaps includinginstructions) into one or more rows making up a memory array within amemory device, such as memory array 751 a of memory device 750 a. Priorto or coincident with writing such data into a row within memory device750 a, CPU 710 is further caused to write marking data into markingbuffer 745 to mark the row within memory array 751 a into which suchdata is being written as having data to be preserved. As a result, whenmemory controller 740 is to command that a row within memory array 751 abe refreshed, memory controller 740 will obtain marking data frommarking buffer 745 to identify a row marked as having data to bepreserved, perhaps the very same row that CPU 710 was just caused tomark as having data to be preserved. Memory controller 740 will thentransmit a row address identifying that row with the refresh command tomemory device 750 a, causing memory device 750 a to carry out a refreshoperation on that specific row within memory array 751 a.

In some embodiments, when computer system 700 is in a reduced powerstate, memory devices making up computer system 700, such as memorydevice 750 a, receive a command from memory controller 740 to enter areduced power state such as a self refresh state. During such aself-refresh state, memory device 750 a must autonomously carry outrefresh operations to refresh rows of memory cells within memory array751 a, and requests to carry out a refresh operation to refresh a givenrow may be generated by a counter at a predetermined interval of timewithin refresh logic 754 a, instead of being received from memorycontroller 740. Since, unlike memory device 250 a of FIG. 2, refreshlogic 754 a of memory device 750 a does not have a marking buffer,memory device 750 a may refresh all rows within memory array 751 a,regardless of which rows within memory array 751 a are marked in markingbuffer 745 as having data to be preserved, and which rows are not. Thismay be necessitated by the need to conserve power by ceasing at leastsome forms of interaction between memory controller 740 and memorydevice 750 a, as is normally done as part of entering a self-refreshstate, as would be known to those skilled in the art.

The invention has been described in conjunction with the preferredembodiment. It is evident that numerous alternatives, modifications,variations and uses will be apparent to those skilled in the art inlight of the foregoing description. It will be understood by thoseskilled in the art that the present invention may be practiced insupport of various types of electronic devices with various possiblememory devices in which the memory cells repeatedly require some form of“refreshing” or other regular maintenance activity in order to preventthe loss of data. It will also be understood by those skilled in the artthat the present invention may be practiced in support of electronicdevices other than computer systems such as audio/video entertainmentdevices, controller devices in vehicles, appliances controlled byelectronic circuitry, etc.

1. An apparatus comprising: a memory array having a plurality of memorycells organized into a plurality of rows of multiple memory cells; amarking buffer storing an indication of which rows of memory cellswithin the memory array are marked as having data to be preserved; and arefresh logic to selectively refresh a row of memory cells if the row ismarked in the marking buffer as having data to be preserved.
 2. Theapparatus of claim 1, further comprising an interface to receive acommand to carry out a refresh operation on a row of memory cells. 3.The apparatus of claim 2, wherein the interface is configured to receivea value accompanying the command to carry out a refresh operationidentifying a specific row of memory cells on which to selectively carryout the commanded refresh operation.
 4. The apparatus of claim 2,wherein the refresh logic further comprises a counter to provide a valueidentifying a specific row of memory cells on which to selectively carryout the commanded refresh operation in response to receiving the commandto carry out a refresh operation on a row of memory cells.
 5. Theapparatus of claim 1, further comprising: an interface to receive acommand to enter a reduced power state in which commands to carry out arefresh operation are not accepted from an external device; and acounter to provide a value identifying a specific row of memory cells onwhich to selectively carry out a refresh operation in response to thepassage of a predetermined interval of time.
 6. The apparatus of claim1, wherein the marking buffer is comprised of one or more rows of memorycells comprising the memory array.
 7. An apparatus comprising: a CPU; amemory device having a plurality memory cells organized into a pluralityof rows of multiple memory cells, and having an interface to receive acommand to mark a row of memory cells as not having data to bepreserved; and a memory controller coupled to both the CPU and thememory device, and configured to transmit a command to the memory deviceto mark a row of memory cells as not having data to be preserved.
 8. Theapparatus of claim 7, wherein the memory device further comprises arefresh logic that is configured to refrain from refreshing a row ofmemory cells marked as not having data to be preserved despite a requestto refresh that row of memory cells.
 9. The apparatus of claim 8,wherein the memory device receives the request from the memorycontroller to refresh a specific row of memory cells.
 10. The apparatusof claim 8, wherein the refresh logic is comprised of a counter toprovide an address of a row of memory cells to generate a request torefresh that row of memory cells.
 11. The apparatus of claim 7, whereinthe memory controller is further configured to transmit a command to thememory device to mark a row of memory cells as having data to bepreserved and the interface of the memory device is configured toreceive the command to mark a row of memory cells as having data to bepreserved.